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revision 0.1 january 2007 k1b3216b8e - 1 - u t ram preliminary 32mb (2m x 16 bit) u t ram information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is prov ided on as "as is" basis without guar- antee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * samsung electronics reserves the right to c hange products or spec ification without notice.
revision 0.1 january 2007 k1b3216b8e - 2 - u t ram preliminary document title 2mx16 bit multiplexed synchronous burst uni-transistor random access memory revision history revision no. history draft date remark 0.0 initial december 19, 2006 preliminary - design target 0.1 revised january 11, 2007 preliminary - inserted package dimension
revision 0.1 january 2007 k1b3216b8e - 1 - utram table of contents preliminary general description............................................................................................................ ...................1 features ....................................................................................................................... ...............................1 product family........ .............. .............. .............. .............. .............. .............. ........... .......... .........................1 pin descriptions & functio n block diagram..... .............. .............. .............. .............. ............ .........2 terminology description ........................................................................................................ .............2 power up sequence.............................................................................................................. ...................3 mode state machine............................................................................................................. ....................3 absolute maximum ratings .. .............. .............. .............. .............. ........... ........... ............ ........... ............4 recommended dc operating conditions.........................................................................................4 capacitance ......... .............. .............. .............. .............. .............. .............. .............. ......... ............................4 dc and operating characteristics............................................................................................... ....4 mrs (mode register set) ........................................................................................................ ................5 mrs code ....................................................................................................................... ......................... 5 mrs timing waveform (software) ........ .............. .............. .............. .............. ........... ............ ......... 6 par (partial array refresh) mode a/dq[3]~a/dq[0] .... ........................................................................... .. 7 dpd (deep power down) mode a/dq[4] ............................................................................................. ...... 7 burst length a/dq[7]~a/dq[5] & wrap a/dq[12] ....... .............. .............. .............. .............. ........... ......... ... 8 wait configuration a/dq[8] & wait polarity a/dq[13] .. .......................................................................... 8 latency a/dq[11]~a/dq[9]....................................................................................................... .................. 9 driver strength a/dq[17]~a/dq[16] .............................................................................................. ............. 9 opeartion mode (a/dq[15]~a/dq[14]) ............. .............. .............. .............. .............. .............. ......... ... 10 mode1. asynchronous read / asynchronous writ e mode .............. .............. ............... ...... 10 mode2. synchronous burst read / asynchronous write mode ... .............. ............... ...... 11 mode3. synchronous burst read / synchronou s burst write mode .... .............. ......... 12 mode 1 ac operating conditions (asynch. read / asynch. write) .. ........... ........... ............ ......13 timing waveforms (asynch. read / asynch. write).. .............. .............. .............. ............... ...... 14 asynch. read ................................................................................................................... ......................... 14 asynchronous write ............................................................................................................. ................... 15 mode 2 ac operating conditions (synch. read / asynch. write) .... ........... ........... ............ ......16 timing waveforms (sy nch. read / synch. write) . .............. .............. ........... ........... ............ ...... 17 burst read - fixed latency..................................................................................................... .................. 17 burst read - variable latency .... .............................................................................................. ................ 18 burst read stop................................................................................................................ ...................... 19 asynch. write .................................................................................................................. ........................ 20 burst read followed by asynch. wr ite ........................................................................................... ........ 21 asynch. write followed by burst r ead ........................................................................................... ........ 22 mode3. ac operatin g conditions (synch. read / synch. write)...............................................23 timing waveforms (sy nch. read / synch. write) . .............. .............. ........... ........... ............ ...... 24 burst read - fixed latency..................................................................................................... .................. 24 burst read - variable latency .... .............................................................................................. ................ 25 burst read stop................................................................................................................ ...................... 26 burst write.................................................................................................................... ........................... 27 burst write (adv pulse interrupt).............................................................................................. ........... 28 burst read stop & burst write stop ............................................................................................. .... 29 burst read followed by burst writ e ............................................................................................. .......... 30 burst write followed by burst read ............................................................................................. .......... 31 package dimension.............................................................................................................. .....................32 54 ball fine pitch bga(0.75mm ball pitch)............. ......................................................................... .... 32
revision 0.1 january 2007 k1b3216b8e - 1 - u t ram preliminary 2m x 16 bit multiplexed synchronous burst uni-transistor cmos ram general description the world is moving into the mobile multi-media era and theref ore the mobile handsets need bigger & faster memory capacity to handle the multi-media data. samsung?s utram products are desi gned to meet all the request from the various customers who want to cope with the fast growing mobile market. utram is the perfect solution for the mobile market with its low cost, high d en- sity and high performance feature. k1 b3216b8e is fabricated by samsung s advanced cmos technology using one transistor memory cell. the device supports the tr aditional sram like asynchronous operat ion (asynchronous page read and asynchronous write), the nor flash like synchronous o peration (synchronous burst read and asynchronous write) and the fully synchronous operation (synchronous burst read and synchronous burst write) . these three operation modes are defined through the mode reg- ister setting. the device also supports the special features for the standby power saving. those are the partial array refresh(par) mode, deep power down(dpd) mode and internal tc sr (temperature compensated self refresh). the optimiza- tion of output drive strength is possible through the mode regi ster setting to adjust for the different data loadings. through this drive strength optimization, the dev ice can minimize the noise generated on the data bus during read operation. features ? process technology: cmos ? organization: 2m x 16 bit ? multiplexed address and data bus ? power supply voltage: 1.7v~1.95v ? three state outputs ? supports mrs (mode register set) - software set up ? supports power saving modes - par (partial array refresh) - dpd (deep power down) - internal tcsr (temperature compensated self refresh) ? supports driver strength optimization ? k1b3216b8e supports - asynchronous read/ asynchronous write - synchronous burst read / asynchronous write - synchronous burst read / synchronous burst write ? synchronous burst operation - max. clock frequency : 104mhz - fixed and variable read latency - 4 / 8 / 16 / 32 and continuous burst - wrap / no-wrap - latency :4(variable) @ 104mhz 3(variable) @ 80mhz 2(variable) @ 66mhz - burst stop - burst read suspend - burst write data masking product family 1) mode 1: asynchronous read/ asynchronous write mode 2: synchronous burst read/ asynchronous write mode 3: synchronous burst read/ synchronous burst write product family operating mode 1) operating temp. vcc range speed current consumption standby (i sb1 , max.) operating (i cc2 , max.) k1b3216b8e-i mode 1 mode 2 mode 3 industrial(-40~85 c) 1.7~1.95v 104mhz tbd < 85 c tbd < 40 c tbd
revision 0.1 january 2007 k1b3216b8e - 2 - u t ram preliminary pin descriptions & function block diagram terminology description name function type description clk clock input synchronizes the memory to the system operating frequency during synchronous operations. commands are referenced to clk. adv address valid input indicates that a valid address is present on the address inputs. addresses can be latched on the rising edge of adv during asynchronous read and write oper- ations. ps mode register set input ps low enables either par or dpd to be set. cs chip select input cs low enables the chip to be active cs high disables the chip and puts it into standby mode or deep power down mode. oe output enable input enables the output buffers when low. when oe is high, the output buffers are disabled. we write enable input we low enables the chip to start writing the data lb lower byte (i/o 0 ~ 7 ) input ub ( lb ) low enables upper byte (lower byte) to allow data input/output from i/o buffers. ub upper byte (i/o 8 ~ 15 ) input a16~a20 address 16 ~ address 20 input inputs for addresses during read and write operations. addresses are inter- nally latched during read and write cycles. a/dq0~a/dq15 address and data inputs / outputs input/output address and data i/os: these pins are multiplexed address/ data bus. v cc voltage source power device power supply. power supply for device core operation. v ccq i/o voltage source power i/o power supply. power supply for input/output buffers. v ss ground source gnd ground for device core operation v ssq i/o ground source gnd ground for input/output buffers wait valid data indicator output the wait signal is output signal indicating the status of the data on the bus whether or not it is valid. wait is asserted when a burst crosses a word-line boundary. wait is asserted and should be ignored during asynchronous and page mode operations. 54-fbga - 6.00 x 8.00 top view (ball down) lb oe ps a/dq8 ub cs a/dq0 a/dq9 a/dq10 a/dq1 a/dq2 vssq a/dq11 a/dq3 vcc vccq a/dq12 a/dq4 vss a/dq14 a/dq13 a/dq5 a/dq6 a/dq15 we a/dq7 wait clk adv a b c d e f g h j 123456 rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu rfu a16 a17 a18 a19 a20 rfu rfu rfu rfu clk gen. row select a/dq 0 ~a/dq 7 data cont data cont data cont a/dq 8 ~a/dq 15 v cc v ss i/o circuit we oe ub cs lb control logic adv row addresses wait ps clk v ccq memory array column address column select pre-charge circuit v ssq
revision 0.1 january 2007 k1b3216b8e - 3 - u t ram preliminary power up sequence after v cc and v ccq reach minimum operating voltage(1.7v), drive cs high first and then drive ps high. then the device gets into the power up mode. wait for minimum 150 s to get into the normal operation mode. during the power up mode, the standby cur- rent can not be guaranteed. to get the stable standby current leve l, at least one cycle of active operation should be implement ed regardless of wait time duration. to get the appropriate device operation, be sure to keep the following power up sequence. mode1 (asynchronous read/ asynchronous write) is set up after power up, but this mode is not always guaranteed. mode state machine 1) refer to mrs(mode register set). ~ ~ v cc v cc(min) ps cs min. 0ns min. 0ns ~ ~ v ccq v ccq(min) 150us cs =v ih cs =v il ps =v ih power on initial state (wait 150 s) active cs =v ih ps =v ih ps =v il dpd mode par mode ps =v il ps =v ih ps =v ih mode register set 1) ps =v ih standby mode
revision 0.1 january 2007 k1b3216b8e - 4 - u t ram preliminary absolute maximum ratings 1) stresses greater than "absolute maximum ratings" may cause permanent damage to the device. functional operation should be re stricted to be used under recommended operating condition. exposure to absolute maximum rating conditions longer than 1 second may affect reli ability. recommended dc operating conditions 1. t a =-40 to 85 c, otherwise specified. 2. overshoot: v ccq +1.0v in case of pulse width 20ns. overshoot is sampled, not 100% tested. 3. undershoot: -1.0v in case of pulse width 20ns. undershoot is sampled, not 100% tested. capacitance dc and operating characteristics 1. i sb1 is measured after 60ms after cs high. clk should be fixed at high or at low. 2. full array partial refresh current(i sbp ) is same as standby current(i sb1 ). 3. internal tcsr (temperature compensated self re fresh) is used to optimize refresh cycle below 40 c. 4. i io =0ma; this parameter is specified with the output s disabled to avoid external loading effects. 5. v in =0v; all inputs should not be toggle. 6. clock should not be inserted between adv low and we low during write operation. item symbol ratings unit voltage on any pin relative to vss v in , v out -0.2 to v ccq +0.3v v power supply voltage relative to vss v cc , v ccq -0.2 to 2.5v v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c item symbol min typ max unit power supply voltage(core) v cc 1.7 1.8 1.95 v power supply voltage(i/o) v ccq 1.7 1.8 1.95 v ground v ss , v ssq 00 0v input high voltage v ih v ccq -0.4 - v ccq +0.2 2) v input low voltage v il -0.2 3) -0.4v item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 8 pf item symbol test conditions min typ max unit input leakage current i li v in =vss to v ccq -1 - 1 a output leakage current i lo cs =v ih , ps =v ih , oe =v ih or we =v il , v io =vss to v ccq -1 - 1 a average operating current(async) i cc2 6) cycle time=70ns, i io =0ma 4) , 100% duty, cs =v il , ps =v ih , v in =v il or v ih --tbdma average operating current(sync) i cc3 burst length 4, latency 5, 104mhz, i io =0ma 4) , address transi- tion 1 time, cs =v il , ps =v ih , v in =v il or v ih --tbdma output low voltage v ol i ol =0.2ma - - 0.2 v output high voltage v oh i oh =-0.2ma 1.4 - - v standby current(cmos) i sb1 1) cs v ccq -0.2v, ps v ccq -0.2v, other inputs=vss or v ccq (toggle is not allowed) 5) < 40 c--tbd a < 85 c--tbd a partial refresh current i sbp 2) ps 0.2v, cs v ccq -0.2v, other inputs=vss or v ccq (toggle is not allowed) 5) < 40 c 1/2 block - - tbd a 1/4 block - - tbd < 85 c 1/2 block - - tbd a 1/4 block - - tbd deep power down current i sbd ps 0.2v, cs v ccq -0.2v, other inputs=vss or v ccq (toggle is not allowed) 5) < 85 c--tbd a (f=1mhz, t a =25 c)
revision 0.1 january 2007 k1b3216b8e - 5 - u t ram preliminary mrs (mode register set) the mode registers store the values for the various modes to make utram suitable for a various applications through mrs. the mode registers have lots of fields and eac h field consists of several options. refer to the table below for detailed mode regis ter setting. a19~a20 addresses are "don?t care" in mode register setting. mrs code mrs code consists of 12 categories and several options in each category. rars, para, par and dpd are related to power sav- ing, bl, wc, latency, wrap, wp, ms and il are related to bus operation and ds is related to device output impedance. mode register setting according to field of function [note] - a19~a20 addresses are "don?t care" & reserved for future use. - the modes are set automatically to defaul t modes which are async. read and async. wr ite/ dpd disable / par disable after powe r up or dpd exit. - mode change rules. mode1(2) to mode3 : 1 dummy write(to any address with any data) is necessary before setting mode3 * dummy write: dummy write timing is just the same with normal write timing. it is necessary because ?late write? i s applied to asynchronous write as in mode1(2). * late write: the data that is latched in previous write cycle is written in the addres s that is also latched in previ ous write cycle when write starts. and current data and address are latched when write ends. (we high or cs high, whichever comes first) mode3 to mode1(2) : 1 dummy write is necessary before setting mode1(2) * dummy write: the data and the address should be the same with those which are used during mode1(2) to mode3 transiti on. 1) wp[0]; the data is available when wait signal is high. all the timings in this spec are illustrated based on this mode. wp[1]; the data is available when wait signal is low. 2) refresh command will be denied during continuous operation. cs low should not be longer than tbc(max. 2.5us) address a18 a17~a16 a/dq15~a/dq14 a/dq13 a/dq12 a/dq11~a/dq9 a/dq8 a/dq7~a/dq5 a/dq4 a/dq3 a/dq2 a/dq1~a/dq0 function il ds ms wp wrap latency wc bl dpd par para pars initial latency driver strength mode select a18 il a17 a16 ds a/dq15 a/dq14 ms 0 fixed 0 0 full drive 0 0 mode 1 (async. read / async. write) 1 variable 0 1 1/2 drive 0 1 mode 2 (sync. burst read / async. write) 1 0 1/4 drive 1 0 mode 3 (sync. burst read / sync. burst write) wait polarity wrap latency count wait configuration burst length a/dq13 wp 1) a/dq12 wrap a/dq11 a/dq10 a/dq9 latency a/dq8 wc a/dq7 a/dq6 a/dq5 bl 0 low enable 0 wrap 10020 one clock prior 0104 word 1 high enable 1 no-wrap 0 0 0 3 1 at data 0 1 1 8 word 0014 100 16 word 010 5 10132 word 0116 111 continuous 2) 1017 1108 1119 deep power down partial array refresh par array par size a/dq4 dpd a/dq3 par a/dq2 para a/dq1 a/dq0 pars 0 dpd enable 0 par enable 0 bottom array 0 0 full array 1 dpd disable 1 par disable 1 top array 1 0 1/2 array 1 1 1/4 array
revision 0.1 january 2007 k1b3216b8e - 6 - u t ram preliminary mrs timing waveform (software) software mrs timing consists of 5 read cyc les. each cycle is normal read cycle. cs pin should be toggling between cycles. 1st, 2nd and 3rd cycle should be 1fffff(h), 4th cycle should be 1ffeff(h) and 5th cycle should be mrs code note) above timing and address condition should not be used in the normal operation. the above condition should be used only fo r the mode regis- ter setting purpose. ac characteristics parameter list symbol min max units parameter list symbol min max units adv setup time to clock t advs 3 - ns read cycle time t rcm 70 - ns adv hold time from clock t advh 2-ns cs high time t chm 10 - ns address setup time to clock t as(b) 3-ns cs low time t clm 60 - ns address hold time from clock t ah(b) 2-ns address t rcm t chm cs t clm 1ff f ff 1ff f ff 1ff f ff 1ff e ff mrs code oe we asynch. mode clock, adv , ub and lb = don?t care, wait =high-z, ps =v ih t advs t advh t as(b) address t rcm t chm cs t clm 1ff f ff 1ff f ff 1ff f ff 1ff e ff mrs code oe we t ah(b) clk adv synch. mode ub and lb = don?t care, ps =v ih
revision 0.1 january 2007 k1b3216b8e - 7 - u t ram preliminary par (partial array refres h) mode a/dq[3]~a/dq[0] user can select half array, a fourth array as active memory ar ray. the active memory array is periodically refreshed(data store d), whereas the disabled array is not going to be refreshed and so the previously stored data will be invalid. when re-enabling add i- tional portions of the array, the new portions ar e available immediately upon writing to the mrs. par mode execution; 1) mode register setting into par enable(a/dq3=0) dpd enabled setting(a/dq4=0) has higher priority to par enabled setting(a/dq3=0). a/dq4=1 is necessary to use par mode. 2) par mode enter; keep ps signal at v il for longer than 0.5 s during standby mode (mode register: a/dq4=1 & a/dq3=0). 3) par mode exit; the device returns to the standby mode when ps signal goes to v ih during par mode. * mode register values are not changed after the device has been to par mode. dpd (deep power down) mode a/dq[4] the deep power down mode disables all the refresh related ac tivities. this mode can be used when the system needs to save power. the data become invalid when dpd mode is executed. dpd mode execution ; 1) mode register setting into dpd enable(a/dq4=0) 2) dpd mode enter; keep ps signal at v il for more than 0.5 s during standby mode (mode register: a/dq4=0). 3) dpd mode exit; the device returns to initial state when ps signal goes to v ih during dpd mode. wake up sequence is needed for the device to do normal operation. * mode register values are initialized to default value after the device has been to dpd mode. default modes are async. read and async. write / dpd disable / par disable. standby mode characteristics 1. only the data in the selected blocks are valid 2. par array can be selected through mode register set 3. standby mode is supposed to be set up after at least one active operation after power up. i sb1 is measured after 60ms from the time when standby mode is set up. power mode address (bottom array) 2) address (top array) 2) memory cell data standby 3) (i sb1 , <40 c) standby 3) (i sb1 , <85 c) wait time( s) standby(full array) 000000h ~ 1fffffh 000000h ~ 1fffffh valid 1) tbd tbd 0 partial refresh(1/2 block) 000000h ~ 0fffffh 100000h ~ 1fffffh valid 1) tbd tbd 0 partial refresh(1/4 block) 000000h ~ 07ffffh 180000h ~ 1fffffh valid 1) tbd tbd 0 deep power down 000000h ~ 1fffffh invalid tbd tbd 150 normal operation ps cs 0.5 s 150 s dpd mode execution and exit par mode execution and exit 0ns(min) deep power down wake up normal operation normal operation ps cs 0.5 s(min) 0ns(min) par mode normal operation (min) (min)
revision 0.1 january 2007 k1b3216b8e - 8 - u t ram preliminary burst length a/dq[7]~a/ dq[5] & wrap a/dq[12] the device supports 4 word, 8 word, 16 word, 32 word and conti nuous burst read or write. and wrap & no-wrap are supported for burst sequence. 1. continuous burst mode needs to meet tbc(max. 2.5us) parameter. wait configuration a/dq[8] & wait polarity a/dq[13] the wait signal is output signal indicating the status of t he data on the bus whether or not it is valid. wait configuration is to decide the timing when wait asserts or desserts. wait asserts (or desserts) one clock prior to the data when a/dq8 is set to 0. (wait asserts (or desserts) at data clock when a/dq8 is set to 1). wait polarity is to decide the wait signal level at which data is valid or invalid. data is valid if wait signal is high when a/dq13 is set to 0. (data is valid if wait signal is low when a/dq13 is set to 1). all the timing diagrams in this spec are illust rated based on following setup; a/dq[13]:0 and a/dq[8]:0. below timing shows wait signal?s movement when word boundary crossing happens in no-wrap mode. burst address sequence(decimal) mode start 4 word 8 word 16 word 32 word wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0 - 1 - 2 - 3 - 4 - 5 ~ 26-27-28-29-30-31 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1 - 2 - 3 - 4 - 5 - 6 ~ 27-28-29-30-31 - 0 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2 - 3 - 4 - 5 - 6 - 7 ~ 28-29-30-31 - 0 - 1 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3 - 4 - 5 - 6 - 7 - 8 ~ 29-30-31- 0 - 1 - 2 ~ ~~ ~ 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7 - 8 - 9 - 10- 11- 12 ~ 2 - 3 - 4 - 5 - 6 ~ ~~ 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20 ~ 10- 11- 12- 13- 14 ~ ~ 31 31- 0 - 1 - 2 - 3 - 4 ~ 25-26-27-28-29-30 no- wrap 0 0-1-2-3 0- 1- 2- 3- 4- 5- 6 -7 0- 1- 2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15 0 - 1 - 2 - 3 - 4 - 5 ~ 26-27-28-29-30-31 1 1-2-3-4 1- 2- 3- 4- 5- 6- 7- 8 1- 2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16 1 - 2 - 3 - 4 - 5 - 6 ~ 27-28-29-30-31-32 2 2-3-4-5 2- 3- 4- 5- 6- 7- 8- 9 2- 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16-17 2 - 3 - 4 - 5 - 6 - 7 ~ 28-29-30-31-32-33 3 3-4-5-6 3- 4- 5- 6- 7- 8- 9-10 3- 4- 5- 6- 7- 8- 9- 10- 11- 12-13-14-15-16-17-18 3 - 4 - 5 - 6 - 7 - 8 ~ 29-30-31-32-33-34 ~ ~~ ~ 7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22 7 - 8 - 9 - 10-11-12 ~ 33-34-35-36-37-38 ~ ~~ 15 15-16-17-18-19-20-21-22-23-24-25-26-27-28-29-30 15-16-17-18-19-20 ~ 41-42-43-44-45-46 ~ ~ 31 31-32-33-34-35-36 ~ 57-58-59-60-61-62 12345678910111213 adv clock d253 d254 0 d255 d256 wait a/dq d257 d258 d259 de-assertion assertion de-assertion 1clk 1clk 1clk wait de-assertion assertion de-assertion no-wrap. word-line crossing. latency : 2. wp : low enable a/dq[8]:0 a/dq[8]:1 word-line crossing period (only exists in no-wrap mode or continuous mode) d260 d261 d262 valid address
revision 0.1 january 2007 k1b3216b8e - 9 - u t ram preliminary latency a/dq[11]~a/dq[9] the latency stands for the number of clocks before the first data available from the burst command. 1) delayed latency should be taken when refresh is required or when burst read newly starts by adv interrupt during burst read operation. driver strength a/dq[17]~a/dq[16] the optimization of output driver strength is possible to adjust for the different data loadings. the device can minimize the n oise generated on the data bus during read operation. the device suppor ts full, 1/2 and 1/4 driver strength. the device?s default mo de is 1/2 driver strength. 1. impedance values are typical values, not 100% tested. item upto 66mhz upto 80mhz upto 104mhz fixed variable fixed variable fixed variable latency set(a/dq11:a/dq10:a/dq9) 4(0:0:1) 2(1:0:0) 5(0:1:0) 3(0:0:0) 7(1:0:1) 4(0:0:1) read latency(min) 4 2 / 4 1) 5 3 / 5 1) 7 4 / 7 1) 1st read data fetch clock 5th 3rd / 5th 1) 6th 4th / 6th 1) 8th 5th / 8th 1) write latency(min) 22334 4 1st write data loading clock 3rd 3rd 4th 4th 5th 5th driver strength full 1 / 2 1 / 4 impedance(typ.) 40 ? 90 ? 150 ? adv clock a/dq a/dq latency 4 (burst length:8) latency 4 (burst length:8) 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th clock d0 d1 d2 d3 d4 d5 d6 d7 q0 q1 q2 q3 q4 q5 q6 q7 a/dq dq0 a/dq latency 2 (burst length: 8) latency 2 (burst length: 8) dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 d1 d2 d3 d4 d5 d6 d7 (read/write) delayed latency should be taken when refresh is required or when burst read newly starts by adv interrupt during burst read operation. variable latency - a/dq[18]:1 fixed latency - a/dq[18]:0 (read) (write) (read) valid address valid address valid address valid address
revision 0.1 january 2007 k1b3216b8e - 10 - u t ram preliminary opeartion mode (a/dq[15]~a/dq[14]) mode1. asynchronous read / asynchronous write mode asynchronous read operation asynchronous read operation starts when cs , oe and ub or lb are asserted. first data come out after random access time(taa) but second, third and fourth data come out after page access time(tpa) when using the page addresses (a/dq0, a/dq1). ps and we should be de-asserted during read operation. clock is don?t care during read operation and wait is hi-z. asynchronous write operation asynchronous write operation starts when cs , we and ub or lb are asserted. ps and should be de-asserted during write oper- ation. clock, oe are don?t care during write operation and wait signal is hi-z. addr. cs ub , lb we a/dq asynchronous write asynchronous read addr. cs ub , lb oe a/dq address high-z data address adv address data address adv (oe high, wait high-z, clock don?t care) (we high, wait high-z, clock don?t care) functional description 1. x means "don?t care". x should be low or high state. 2. in asynchronous mode, clock is ignored. clock should be low or high state. 3. /wait pin is high-z in asynchronous mode. cs oe we lb ub adv a/dq0~15 a16 ~ a20 mode power h x 1) x 1) x 1) x 1) x 1) high-z x 1) deselected standby lhh x 1) x 1) h high-z x 1) output disabled active l x 1) x 1) hh x 1) high-z x 1) output disabled active l h h h h add. input add. input address input active llhlhh dout x 1) lower byte read active llhhlh dout x 1) upper byte read active llhllh dout x 1) word read active lhllhh din x 1) lower byte write active lhlhlh din x 1) upper byte write active lhlllh din x 1) word write active
revision 0.1 january 2007 k1b3216b8e - 11 - u t ram preliminary mode2. synchronous burst read / asynchronous write mode synchronous burst read operation burst read command is implemented when adv is detected low at clock rising edge. we should be de-asserted during burst read, burst operation re-starts whenever adv is detected low at clock rising ed ge even in the middle of operation. variable latency allows the utram to be configured for minimum latency at high frequencies, but the controller must monitor wai t to detect any conflict with refresh cycles. asynchronous write operation asynchronous write operation starts when cs , we and ub or lb are asserted. ps and should be de-asserted during write oper- ation. clock, oe are don?t care during write operation and wait signal is hi-z. functional description 1. x means "don?t care". x should be low or high state. 2. /wait is device output signal so does not have any affect to the mode definition. please refer to each timing diagram for /w ait pin function. cs ps oe we lb ub a/dq0~7 a/dq8~15 clk adv mode power hh x 1) x 1) x 1) x 1) high-z high-z x 1) x 1) deselected standby hl x 1) x 1) x 1) x 1) high-z high-z x 1) x 1) deselected par lhhh x 1) x 1) high-z high-z x 1) h output disabled active lh x 1) x 1) h h high-z high-z x 1) h output disabled active lh x 1) h x 1) x 1) address address read command active l h l h l h dout high-z h lower byte read active l h l h h l high-z dout h upper byte read active l h l h l l dout dout h word read active l h h l l h din high-z x 1) h lower byte write active l h h l h l high-z din x 1) h upper byte write active l h h l l l din din x 1) h word write active clk adv addr. ub , lb oe a/dq cs wait 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 synchronous burst read clk adv addr. ub , lb we a/dq cs asynchronous write (ps high, oe high, wait high-z, clock don?t care) valid data (latency 3, bl 4, wp : low enable, ps high, we high ) 15
revision 0.1 january 2007 k1b3216b8e - 12 - u t ram preliminary mode3. synchronous burst read / synchronous burst write mode synchronous burst read operation burst read command is implemented when adv is detected low at clock rising edge. we should be de-asserted during burst read, burst read operation re-starts whenever adv is detected low at cloc k rising edge even in the middle of burst read opera- tion. variable latency allows the utram to be configured for mi nimum latency at high frequencies, but the controller must monit or wait to detect any conflict with refresh cycles. synchronous burst write operation burst write command is implemented when adv & we are detected low at clock rising edge. burst write operation re-starts whenever adv is detected low at clock rising edge even in the middle of burst write operation. write operations always use fixed latency. functional description 1. x means "don?t care". x should be low or high state. 2. /wait is device output signal so does not have any affect to the mode definition. please refer to each timing diagram for /w ait pin function. cs ps oe we lb ub i/o0~7 i/o8~15 clk adv mode power hh x 1) x 1) x 1) x 1) high-z high-z x 1) x 1) deselected standby hl x 1) x 1) x 1) x 1) high-z high-z x 1) x 1) deselected par lhhh x 1) x 1) high-z high-z x 1) h output disabled active lh x 1) x 1) h h high-z high-z x 1) h output disabled active lh x 1) h x 1) x 1) high-z high-z read command active l h l h l h dout high-z h lower byte read active l h l h h l high-z dout h upper byte read active l h l h l l dout dout h word read active lh x 1) l x 1) x 1) high-z high-z write command active lhh x 1) l h din high-z h lower byte write active lhh x 1) h l high-z din h upper byte write active lhh x 1) l l din din h word write active synchronous burst write (latency 3, bl 4, wp : low enable) clk adv addr. ub , lb we a/dq cs wait 0 1 2 3 4 5 6 7 8 9 10 11 12 13 (ps high, oe high ) clk adv addr. ub , lb oe a/dq cs wait 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 synchronous burst read (latency 3, bl 4, wp : low enable) (ps high, we high ) 15 14
revision 0.1 january 2007 k1b3216b8e - 13 - u t ram preliminary mode 1 ac operating conditions (asynch. read / asynch. write) test conditions (test load and test input/output reference) input pulse level: 0.2 to v ccq -0.2v input rising and falling time: 3ns input and output reference voltage: 0.5 x v ccq output load: c l =30pf v cc :1.7v~1.95v t a : -40 c~85 c ac characteristics 1. t wp (min)=70ns for continuous write without cs toggling longer than 2.5us 2. the high-z timings measure a 100mv transition from either v oh or v ol toward v ccq x 0.5 3. the low-z timings measure a 100mv transition away from the high-z level toward either v oh or v ol . parameter list symbol speed units min max common cs high pulse width t cshp(a) 10 - ns address set-up time to adv rising t as(a) 7-ns address hold time from adv rising t ah(a) 3-ns adv pulse width low t vp 7-ns asynch. read address access time t aa -70ns adv access time t aadv -70ns cs setup time to adv rising t css(a) 5-ns chip select to output t co -70ns output enable to valid output t oe -20ns ub , lb access time t ba -20ns output enable to low-z output t olz 5-ns chip disable to high-z output t chz 010ns ub , lb disable to high-z output t bhz 0 10 ns output disable to high-z output t ohz 010ns adv high to oe low t advoe 5-ns asynch. write adv setup to end of write t vs 70 - ns chip select to end of write t cw 60 - ns address valid to end of write t aw 60 - ns ub , lb valid to end of write t bw 60 - ns write pulse width t wp 55 1) -ns write recovery time t wr 0-ns data to write time overlap t dw 20 - ns data hold from write time t dh 0-ns cs low to adv high t cvs 7-ns adv high to we low tadvwe 5-ns ac output load circuit vtt=0.5 x vccq 50 ? dout 30pf z0=50 ?
revision 0.1 january 2007 k1b3216b8e - 14 - u t ram preliminary timing waveforms (asynch. read / asynch. write) asynch. read ( ps =vih, we =vih, wait =high-z) 1. t chz and t ohz are defined as the time when the outputs achieve the open circ uit conditions and are not referenced to output voltage levels. 2. in asynchronous read cycle, clock is ignored. t aa t ba t oe t olz t ohz t chz t co cs# ub#/ lb# oe# a/dq[15:0] adv# don?t care undefined t as(a) valid output t aadv t vp t css(a) t cshp(a) t bhz we# v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v ol v oh a[20:16] valid address v il v ih valid address t ah(a) t advoe
revision 0.1 january 2007 k1b3216b8e - 15 - u t ram preliminary asynchronous write notes: 1. the end of the write cycle is controlled by ce #, ub#/lb#, or we#, whichever de-asserts first. a/dq[15:0] v ih v il adv# v ih v il cs# v ih v il ub#/lb# v ih v il we# v ih v il don?t care t as(a) t vs t vp t aw t cw t bw t wp t dw t dh t cvs a[20:16] v ih v il valid address valid address data valid t ah(a) t advwe t cshp(a)
revision 0.1 january 2007 k1b3216b8e - 16 - u t ram preliminary mode 2 ac operating conditions (synch. read / asynch. write) test conditions (test load and test input/output reference) input pulse level: 0.2 to v ccq -0.2v input rising and falling time: 1ns input and output reference voltage: 0.5 x v ccq output load: c l =30pf v cc :1.7v~1.95v t a : -40 c~85 c ac characteristics 1. refresh can not be implemented when tbsadv is in the range of 0ns ~ 13ns. it may cause refresh fail to use the device under that condition over 2.5us without cs toggling. to avoid refresh fail, 13ns for all frequency is needed for tbsadv. 2. the high-z timings measure a 100mv transition from either v oh or v ol toward v ccq x 0.5 3. the low-z timings measure a 100mv transition away from the high-z level toward either v oh or v ol . 1. t wp (min)=70ns for continuous writ e longer than 2.5us without cs toggling. parameter list symbol 66mhz 80mhz 104mhz units min max min max min max synch. burst read clock cycle time t 15 200 12.5 200 9.6 200 ns burst cycle time t bc - 2500 - 2500 - 2500 ns address set-up time to clock t as(b) 5-4-3-ns address hold time from clock t ah(b) 2-2-2-ns adv setup time to clock t advs 5-4-3-ns adv hold time from clock t advh 2-2-2-ns cs setup time to clock t css(b) 5-4-3-ns cs high to adv low (burst stop) t bsadv 1) 00 0ns cs low hold time from clock(burst stop) t cslh 2-2-2-ns cs high pulse width t cshp 5-5-5-ns cs low to wait low t wl -7.5-7.5-7.5ns clock to wait high t wh -11- 9 - 7ns cs high to wait high-z t wz -10-10-10ns ub , lb low to end of latency clock t bel 20 - 20 - 20 - ns oe low to end of latency clock t oel 20 - 20 - 20 - ns ub , lb low to low-z output t blz 5-5-5-ns oe low to low-z output t olz 5-5-5-ns clock rising to data output t cd -11- 9 - 7ns output hold from clock t oh(b) 3-3-3-ns burst end clock to output high-z t hz -10-10-10ns cs high to output high-z t chz -10-10-10ns oe high to output high-z t ohz -10-10-10ns ub , lb high to output high-z t bhz -10-10-10ns adv# high to oe# low t advo 5-4-3-ns parameter list symbol speed units min max asynch. write write cycle time t wc 70 - ns chip select to end of write t cw 60 - ns adv minimum low pulse width t adv 5-ns address set-up time to adv rising t as(a) 5-ns address hold time from adv rising t ah(a) 3-ns cs setup time to adv rising t css(a) 5-ns address valid to end of write t aw 60 - ns ub , lb valid to end of write t bw 60 - ns write pulse width t wp 55 1) -ns write recovery time t wr 0-ns data to write time overlap t dw 20 - ns data hold from write time t dh 0-ns adv# high to we# low t advwe 5-ns ac output load circuit vtt=0.5 x vccq 50 ? dout 30pf z0=50 ?
revision 0.1 january 2007 k1b3216b8e - 17 - u t ram preliminary timing waveforms (synch. read / synch. write) burst read - fixed latency (ps =vih, we =vih, wait =high-z, latency=4, burst length=4, wp=low enable, wc=one clock prior to the data) 1. /wait low(twl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 2. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 3. burst operation should not be longer than tbc(2.5 s) ac characteristics symbol 66mhz 80mhz 104mhz units symbol 66mhz 80mhz 104mhz units min max min max min max min max min max min max t 15 200 12.5 200 9.6 200 ns t blz 5-5-5-ns t bc - 2500 - 2500 - 2500 ns t olz 5-5-5-ns t advs 5-4-3-ns t hz -10-10-10ns t advh 2-2-2-ns t chz -10-10-10ns t as(b) 5-4-3-ns t ohz -10-10-10ns t ah(b) 2-2-2-ns t bhz -10-10-10ns t css(b) 5-4-3-ns t cd -11- 9 - 7 ns t cshp 5-5-5-ns t oh(b) 3-3-3-ns t bel 20 - 20 - 20 - ns t wl - 7.5 - 7.5 - 7.5 ns t oel 20 - 20 - 20 - ns t wh -11- 9 - 7 ns t wz -10-10-10ns t advo 5-4-3-ns 123456789101112131415 adv a[20:16] cs lb , ub a/dq[15:0] oe clk dq0 dq1 dq2 dq3 undefined valid t hz t advs t advh t as(b) t ah(b) t css(b) t t oh(b) wait t blz t bel t oel t olz 0 t wh t wl t wz t chz t ohz t bhz t cshp t wl t wh t bc dq0 undefined t as(b) t ah(b) address valid address valid address valid address undefined t cd t advo
revision 0.1 january 2007 k1b3216b8e - 18 - u t ram preliminary burst read - va riable latency (ps =vih, we =vih , latency=3, burst length=4, wp=low enable, wc=one clock prior to the data) 1. delayed latency should be taken increased w hen refresh is required. refer to latency table. 2. /wait low(twl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 4. burst operation should not be longer than tbc(2.5 s). ac characteristics symbol 66mhz 80mhz 104mhz units symbol 66mhz 80mhz 104mhz units min max min max min max min max min max min max t 15 200 12.5 200 9.6 200 ns t blz 5-5-5-ns t bc - 2500 - 2500 - 2500 ns t olz 5-5-5-ns t advs 5-4-3-ns t hz -10-10-10ns t advh 2-2-2-ns t chz -10-10-10ns t as(b) 5-4-3-ns t ohz -10-10-10ns t ah(b) 2-2-2-ns t bhz -10-10-10ns t css(b) 5-4-3-ns t cd -11- 9 - 7 ns t cshp 5-5-5-ns t oh(b) 3-3-3-ns t bel 20 - 20 - 20 - ns t wl - 7.5 - 7.5 - 7.5 ns t oel 20 - 20 - 20 - ns t wh -11- 9 - 7 ns t wz -10-10-10ns t advo 5-4-3-ns 123456789101112131415 adv a[20:16] cs lb , ub a/dq[15:0] oe clk dq0 dq1 dq2 dq3 undefined t cd valid t hz t advs t advh t css(b) t t oh(b) wait t blz t bel t oel t olz 0 t wh t wl t wz t chz t ohz t bhz t cshp t wl t wh t bc undefined t as(b) t ah(b) t ah(b) t as(b) dq0* latency 3 latency 5 address valid address valid t as(b) t ah(b) address undefined valid address t advo
revision 0.1 january 2007 k1b3216b8e - 19 - u t ram preliminary burst read stop (ps =vih, variable latency=3, burst length=4, wp=low enable, wc=one clock prior to the data) 1. /wait low(twl ) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 2. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 3. refresh can not be implemented when tbsadv is in the range of 0ns ~ 13ns. it may cause refresh fail to use the device under that condition over 2.5us without cs toggling. to avoid refresh fail, 13ns for all frequency is needed for tbsadv. ac characteristics symbol 66mhz 80mhz 104mhz units symbol 66mhz 80mhz 104mhz units min max min max min max min max min max min max tbsadv 0-0-0-ns t cd -11- 9 - 7 ns tcslh 2-2-2-ns t oh(b) 3-3-3-ns t cshp 5-5-5-ns t chz -10-10-10ns t bel 20 - 20 - 20 - ns t wl - 7.5 - 7.5 - 7.5 ns t oel 20 - 20 - 20 - ns t wh -11- 9 - 7 ns t blz 5-5-5-ns t wz -10-10-10ns t olz 5-5-5-ns t advo 5-4-3-ns 1234567891011121314 adv a[20:16] cs lb , ub a/dq[15:0] oe clk dq0 undefined don?t care t advs t advh t css(b) t t oh(b) t chz wait t bel t oel t blz t olz t cslh t cshp 0 high-z t wl t wh t wz t wl dq1 t bsadv t as(b) t ah(b) t css(b) t as(b) t ah(b) t advo valid address valid address valid address valid address
revision 0.1 january 2007 k1b3216b8e - 20 - u t ram preliminary asynch. write (ps =vih, oe =vih, wait =high-z) ub , lb we a/dq[15:0] t bw t wp t dh t dw data valid adv a[20:16] cs t as(a) t ah(a) t css(a) t cw 12345678910111213 clk 0 14 t adv t as(a) t ah(a) t advwe valid address valid address
revision 0.1 january 2007 k1b3216b8e - 21 - u t ram preliminary burst read followed by asynch. write (ps =vih, wait =high-z, variable latency=3) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for sin- gle byte operation or simultaneously asserting ub and lb for word operation. a write ends at the earliest transition when cs goes high or we goes high. the t wp is measured from the beginning of write to the end of write. 2. t aw is measured from the address valid to the end of write. in this address latch type write timing, t wc is same as t aw. 3. t cw is measured from the cs going low to the end of write. 4. t bw is measured from the ub and lb going low to the end of write. 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv a[20:16] cs lb , ub oe clk dq0 t hz t css(b) t t oh(b) don?t care t bel t oel t advs t advh 14 15 16 17 18 21 dq1 dq3 dq2 we t css(a) a/dq[15:0] t dh t dw data valid 0 t wp t cw t bw t bc wait t wh t wl t wz t adv t as(b) t ah(b) t as(a) t ah(a) latency 3 t wl t wz high-z t as(b) t ah(b) valid address valid address valid address t as(a) t ah(a) valid address t advo t advwe
revision 0.1 january 2007 k1b3216b8e - 22 - u t ram preliminary asynch. write followed by burst read (ps =vih, variable latency=3,burst length=4, wp=low enable, wc=one clock prior to the data) 1. /wait low(twl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 2. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 3. burst operation should not be longer than tbc(2.5 s) 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv a[20:16] cs lb , ub oe clk dq0 t cd valid t hz valid t css(a) t t oh(b) t bel t oel t advs t advh 14 15 16 17 18 0 dq1 dq3 dq2 we t css(b) a/dq[15:0] t wp t bw t dh t dw data valid t aw t cw t adv wait high-z t wh t wl t wz t bc t as(a) t ah(a) t as(b) t ah(b) t advwe t advo
revision 0.1 january 2007 k1b3216b8e - 23 - u t ram preliminary mode3. ac operating conditions (synch. read / synch. write) test conditions (test load and test input/output reference) input pulse level: 0.2 to v cc -0.2v input rising and falling time: 1ns input and output reference voltage: 0.5 x v cc output load: c l =30pf v cc :1.7v~1.95v t a : -40 c~85 c ac characteristics 1. refresh can not be implemented when t bsadv is in the range of 0ns ~ 13ns. it may cause refr esh fail to use the device under that condition over 2.5us without cs toggling. to avoid refresh fail, 13ns for all frequency is needed for t bsadv . 2. the high-z timings measure a 100mv transition from either v oh or v ol toward v ccq x 0.5 3. the low-z timings measure a 100mv transition away from the high-z level toward either v oh or v ol . 1. refresh can not be implemented when t beadv is in the range of 0ns ~ 13ns. it may cause refr esh fail to use the device under that condition over 2.5us without cs toggling. to avoid refresh fail, 13ns for all frequency is needed for t beadv . parameter list symbol 66mhz 80mhz 104mhz units min max min max min max burst operation (common) clock cycle time t 15 200 12.5 200 9.6 200 ns burst cycle time t bc - 2500 - 2500 - 2500 ns address set-up time to clock t as(b) 5-4-3-ns address hold time from clock t ah(b) 2-2-2-ns adv setup time to clock t advs 5-4-3-ns adv hold time from clock t advh 2-2-2-ns cs setup time to clock t css(b) 5-4-3-ns cs high to new adv low (burst stop) t bsadv 0-0-0-ns cs low hold time from clock(burst stop) t cslh 2-2-2-ns cs high pulse width t cshp 5-5-5-ns cs low to wait low t wl - 7.5 - 7.5 - 7.5 ns clock to wait high t wh -11- 9 - 7ns cs high to wait high-z t wz -10-10-10ns burst read operation ub , lb low to end of latency clock t bel 20 - 20 - 20 - ns oe low to end of latency clock t oel 20 - 20 - 20 - ns ub , lb low to low-z output t blz 5-5-5-ns oe low to low-z output t olz 5-5-5-ns clock rising to data output t cd -11- 9 - 7ns output hold from clock t oh(b) 3-3-3-ns burst end clock to output high-z t hz -10-10-10ns cs high to output high-z t chz -10-10-10ns oe high to output high-z t ohz -10-10-10ns ub , lb high to output high-z t bhz -10-10-10ns adv# high to oe# low t advo 5-4-3-ns burst write operation we set-up time to clock t wes 5-4-3-ns we hold time from clock t weh 2-2-2-ns ub , lb set-up time to clock t bs 5-4-3-ns burst end clock to new adv low t beadv 0-0-0-ns ub , lb hold time from clock t bh 2-2-2-ns byte masking set-up time to clock t bms 5-4-3-ns byte masking hold time from clock t bmh 2-2-2-ns write data set-up time to clock t ds 5-4-3-ns write data hold time from clock t dhc 2-2-2-ns ac output load circuit vtt=0.5 x vccq 50 ? dout 30pf z0=50 ?
revision 0.1 january 2007 k1b3216b8e - 24 - u t ram preliminary timing waveforms (synch. read / synch. write) burst read - fixed latency (ps =vih, we =vih, wait =high-z, latency=4, burst length=4, wp=low enable, wc=one clock prior to the data) 1. /wait low(twl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 2. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 3. burst operation should not be longer than tbc(2.5 s) ac characteristics symbol 66mhz 80mhz 104mhz units symbol 66mhz 80mhz 104mhz units min max min max min max min max min max min max t 15 200 12.5 200 9.6 200 ns t blz 5-5-5-ns t bc - 2500 - 2500 - 2500 ns t olz 5-5-5-ns t advs 5-4-3-ns t hz -10-10-10ns t advh 2-2-2-ns t chz -10-10-10ns t as(b) 5-4-3-ns t ohz -10-10-10ns t ah(b) 2-2-2-ns t bhz -10-10-10ns t css(b) 5-4-3-ns t cd -11- 9 - 7 ns t cshp 5-5-5-ns t oh(b) 3-3-3-ns t bel 20 - 20 - 20 - ns t wl - 7.5 - 7.5 - 7.5 ns t oel 20 - 20 - 20 - ns t wh -11- 9 - 7 ns t wz -10-10-10ns t advo 5-4-3-ns 123456789101112131415 adv a[20:16] cs lb , ub a/dq[15:0] oe clk dq0 dq1 dq2 dq3 undefined valid t hz t advs t advh t as(b) t ah(b) t css(b) t t oh(b) wait t blz t bel t oel t olz 0 t wh t wl t wz t chz t ohz t bhz t cshp t wl t wh t bc dq0 undefined t as(b) t ah(b) address valid address valid address valid address undefined t cd t advo
revision 0.1 january 2007 k1b3216b8e - 25 - u t ram preliminary burst read - va riable latency (ps =vih, we =vih , latency=3, burst length=4, wp=low enable, wc=one clock prior to the data) 1. delayed latency should be taken increased w hen refresh is required. refer to latency table. 2. /wait low(twl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 4. burst operation should not be longer than tbc(2.5 s). ac characteristics symbol 66mhz 80mhz 104mhz units symbol 66mhz 80mhz 104mhz units min max min max min max min max min max min max t 15 200 12.5 200 9.6 200 ns t blz 5-5-5-ns t bc - 2500 - 2500 - 2500 ns t olz 5-5-5-ns t advs 5-4-3-ns t hz -10-10-10ns t advh 2-2-2-ns t chz -10-10-10ns t as(b) 5-4-3-ns t ohz -10-10-10ns t ah(b) 2-2-2-ns t bhz -10-10-10ns t css(b) 5-4-3-ns t cd -11- 9 - 7 ns t cshp 5-5-5-ns t oh(b) 3-3-3-ns t bel 20 - 20 - 20 - ns t wl - 7.5 - 7.5 - 7.5 ns t oel 20 - 20 - 20 - ns t wh -11- 9 - 7 ns t wz -10-10-10ns t advo 5-4-3-ns 123456789101112131415 adv a[20:16] cs lb , ub a/dq[15:0] oe clk dq0 dq1 dq2 dq3 undefined t cd valid t hz t advs t advh t css(b) t t oh(b) wait t blz t bel t oel t olz 0 t wh t wl t wz t chz t ohz t bhz t cshp t wl t wh t bc undefined t as(b) t ah(b) t ah(b) t as(b) dq0* latency 3 latency 5 address valid address valid t as(b) t ah(b) address undefined valid address t advo
revision 0.1 january 2007 k1b3216b8e - 26 - u t ram preliminary burst read stop (ps =vih, variable latency=3, burst length=4, wp=low enable, wc=one clock prior to the data) 1. /wait low(twl ) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 2. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 3. refresh can not be implemented when tbsadv is in the range of 0ns ~ 13ns. it may cause refresh fail to use the device under that condition over 2.5us without cs toggling. to avoid refresh fail, 13ns for all frequency is needed for tbsadv. ac characteristics symbol 66mhz 80mhz 104mhz units symbol 66mhz 80mhz 104mhz units min max min max min max min max min max min max tbsadv 0-0-0-ns t cd -11- 9 - 7 ns tcslh 2-2-2-ns t oh(b) 3-3-3-ns t cshp 5-5-5-ns t chz -10-10-10ns t bel 20 - 20 - 20 - ns t wl - 7.5 - 7.5 - 7.5 ns t oel 20 - 20 - 20 - ns t wh -11- 9 - 7 ns t blz 5-5-5-ns t wz -10-10-10ns t olz 5-5-5-ns 1234567891011121314 adv a[20:16] cs lb , ub a/dq[15:0] oe clk dq0 undefined don?t care valid valid t advs t advh t css(b) t t oh(b) t chz wait t bel t oel t blz t olz t cslh t cshp 0 high-z t wl t wh t wz t wl dq1 t bsadv t as(b) t ah(b) t css(b) valid t as(b) t ah(b) valid t advo
revision 0.1 january 2007 k1b3216b8e - 27 - u t ram preliminary burst write (ps =vih, oe =vih, variable latency=3, burst length=4, wp=low enable, wc=one clock prior to the data) 1. refresh can not be implemented when t beadv is in the range of 0ns ~ 13ns. it may cause refr esh fail to use the device under that condition over 2.5us without cs toggling. to avoid refresh fail, 13ns for all frequency is needed for t beadv . 2. /wait low(twl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising.the data starts after set latency from the last clock rising. 4. burst operation should not be longer than tbc(2.5 s) ac characteristics symbol 66mhz 80mhz 104mhz units symbol 66mhz 80mhz 104mhz units min max min max min max min max min max min max t cshp 5-5-5-ns t ds 3-3-3-ns t bs 5-4-3-ns t dhc 2-2-2-ns t bh 2-2-2-ns t wl - 7.5 - 7.5 - 7.5 ns t bms 5-4-3-ns t wh -11- 9 - 7 ns t bmh 2-2-2-ns t wz -10-10-10ns t wes 5-4-3-ns t weh 2-2-2-ns 12345678910111213 adv a[20:16] cs lb , ub a/dq[15:0] we clk d0 d1 d2 d3 t advs t advh t css(b) t t dhc wait 0 t wes t weh t ds t dhc t bms t bmh high-z t wl t wh t bs t bh d0 t cshp t wz t wl t wh t beadv t bc t as(b) t ah(b) t as(b) t ah(b) t as(b) t ah(b) t as(b) t ah(b) valid address valid address valid address valid address
revision 0.1 january 2007 k1b3216b8e - 28 - u t ram preliminary burst write (adv pulse interrupt) (ps =vih, oe =vih, variable latency=3, burst length=4, wp=low enable, wc=one clock prior to the data) 1. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 2. /wait low(twl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. burst interrupt is allowable after the first data word written. ac characteristics symbol 66mhz 80mhz 104mhz units symbol 66mhz 80mhz 104mhz units min max min max min max min max min max min max t cshp 5-5-5-ns t ds 5-4-3-ns t bs 5-4-3-ns t dhc 2-2-2-ns t bh 2-2-2-ns t wl - 7.5 - 7.5 - 7.5 ns t bms 5-4-3-ns t wh -11- 9 - 7 ns t bmh 2-2-2-ns t wz -10-10-10ns t wes 5-4-3-ns t weh 2-2-2-ns 12345678910111213 adv a[20:16] cs lb , ub a/dq[15:0] we clk d0 d1 t advs t advh t as(b) t ah(b) t css(b) t t dhc wait 0 t wes t weh t ds t wl t wh t bs t bh d0 t wl t wh t advs t advh t as(b) t ah(b) d1 d2 d3 t wes t weh t as(b) t ah(b) t as(b) t ah(b) valid address valid address valid address valid address
revision 0.1 january 2007 k1b3216b8e - 29 - u t ram preliminary burst read stop & burst write stop (ps =vih, variable latency=3, burst length=4, wp=low enable, wc=one clock prior to the data) 1. refresh can not be implemented when t beadv is in the range of 0ns ~ 13ns. it may cause refr esh fail to use the device under that condition over 2.5us without cs toggling. to avoid refresh fail, 13ns for all frequency is needed for t beadv . 2. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 3. /wait low(twl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) ac characteristics symbol 66mhz 80mhz 104mhz units symbol 66mhz 80mhz 104mhz units min max min max min max min max min max min max t cshp 5-5-5-ns t ds 5-4-3-ns t bs 5-4-3-ns t dhc 2-2-2-ns t bh 2-2-2-ns t wl - 7.5 - 7.5 - 7.5 ns t bms 5-4-3-ns t wh -11- 9 - 7 ns t bmh 2-2-2-ns t wz -10-10-10ns t wes 5-4-3-ns t bsadv -0-0-0ns t weh 2-2-2-ns t oh(b) 3-3-3-ns 1234567891011121314 adv a[20:16] cs lb , ub a/dq[15:0] oe clk dq0 undefined t cd don?t care t advs t advh t css(b) t t oh(b) t chz wait t bel t oel t blz t olz t cslh t cshp 0 high-z t wl t wh t wz t wl dq1 t bsadv a/dq[15:0] we d0 d1 wait t wl t wh t wh t cslh write t as(b) t ah(b) t css(b) t as(b) t ah(b) undefined undefined t as(b) t ah(b) undefined valid address valid address valid address valid address valid address valid address t advo
revision 0.1 january 2007 k1b3216b8e - 30 - u t ram preliminary burst read followed by burst write (ps =vih, variable latency=3, burst length=4, wp=low enable, wc=one clock prior to the data) 1. /wait low(twl ) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 2. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 3. burst operation should not be longer than tbc(2.5 s) 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv a[20:16] cs lb , ub oe clk t css(b) t don?t care t bel t oel t advs t advh 14 15 16 17 18 21 we t css(b) a/dq[15:0] 0 t bc d1 d3 d2 d0 wait t wh t wl t wz t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh t as(b) t ah(b) dq0 t cd t hz t oh(b) dq1 dq3 dq2 t as(b) t ah(b) valid address valid address valid address valid address t advo
revision 0.1 january 2007 k1b3216b8e - 31 - u t ram preliminary burst write followed by burst read (ps =vih, variable latency=3, burst length=4, wp=low enable, wc=one clock prior to the data) 1. refresh can not be implemented when t beadv is in the range of 0ns ~ 13ns. it may cause refr esh fail to use the device under that condition over 2.5us without cs toggling. to avoid refresh fail, 13ns for all frequency is needed for t beadv . 2. /wait low(twl) : data not available(driven by cs low going edge or adv low going edge) /wait high(twh) : data available(driven by latency-1 clock) /wait high-z(twz) : data don?t care(driven by cs high going edge) 3. multiple clock risings are allowed during low adv period. the data starts after set latency from the last clock rising. 4. burst operation should not be longer than (tbc)2.5 s. high-z 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 adv a[20:16] cs lb , ub oe clk t cd t css(b) t don?t care t bel t oel t advs t advh 14 15 16 17 18 21 we t css(b) a/dq[15:0] t beadv 0 t bc d1 d2 wait t wh t wl t bc t wes t weh t bs t bh t ds t dhc t wz t wl t wh d3 d0 t as(b) t ah(b) valid address valid address t hz t oh(b) dq0 dq1 dq3 dq2 t as(b) t ah(b) valid address valid address t advo
revision 0.1 january 2007 k1b3216b8e - 32 - u t ram preliminary package dimension 54 ball fine pitch bg a(0.75mm ball pitch) 654321 a b c d e f g h c b c1 b c bottom view top view d e1 e c side view a y detail a min typ max a - 0.75 - b 5.90 6.00 6.10 b1 - 3.75 - c 7.90 8.00 8.10 c1 - 6.00 - d 0.40 0.45 0.50 e- -1.00 e1 0.25 - - y- -0.10 b1 #a1 notes. 1. ball counts: 54(9 row x 6 column) 2. ball pitch: (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are 0.050 unless specified beside figure. 4. typ: typical 5. y is coplanarity unit: millimeters e1 j

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